1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a pMOS and an nMOS to activate an impurity implantation region at a high concentration, and to form a gate electrode with a reduced gate leakage current.
2. Description of the Related Art
In the miniaturization of a MOSFET, parasitic resistance and a short channel effect increase along with a reduction in the dimensions of elements, and it is therefore important to form a shallow source/drain region with low resistance. While impurities have to be adequately activated in order to reduce the resistance of an impurity diffusion region, the impurities diffuse due to annealing for activation, so that high-temperature and ultra-rapid annealing is required.
An annealing technique using a flash lamp in which an inert gas such as xenon (Xe) is sealed or using a laser has been considered as means for instantaneously supplying the heat energy necessary for the activation (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2004-63574). These light sources are capable of generating light at a pulse width of a millisecond order, and can therefore activate implanted impurity atoms with little diffusion. Irradiating light energy can be increased to considerably reduce the resistance of a diffusion layer and recover from (e.g., eliminate, remedy) ion implantation defects, such that an improvement in the driving force of the MOSFET can be expected.
However, due to characteristics that enable the instantaneous supply of high heat energy, polysilicon on a gate insulating film easily reaches a high temperature because it does not easily release heat. This leads to a problem that impurities contained in the polysilicon gate diffuse before the heat energy is adequately supplied to a monocrystalline silicon substrate, and the impurities infiltrate into the gate insulating film and deteriorate the breakdown voltage.
One solution to this problem is a method which reduces the amount of impurities ion-implanted into polysilicon. However, a capacitance is formed due to depletion at the bottom of the polysilicon gate, which entails the risk of an increase in the thickness of the effective gate insulating film. That is, there is a trade-off relation between the high-concentration activation of the source/drain region and the suppression of a gate leakage current, and therefore existing ultra-rapid optical annealing techniques have a problem of being unable to ensure a process window in a semiconductor device manufacturing process.
There has therefore been a desire for the provision of a high-efficiency semiconductor device manufacturing method capable of activating impurities implanted in a gate electrode and a semiconductor substrate at a high concentration without increasing a gate leakage current, and which is also capable of expanding a process window in a semiconductor device manufacturing process.